1. Field of the Invention
The present invention relates to an electronic component package and a method of manufacturing the same and an electronic component device and, more particularly, an electronic component package on which an electronic component such as an MEMS element, an optical semiconductor element, or the like is mounted and a method of manufacturing the same and an electronic component device.
2. Description of the Related Art
In the prior art, there is the electronic component package on which the electronic component such as the MEMS element, the optical semiconductor element, or the like is mounted. As such electronic component package, some packages have such a structure that a cavity in which the electronic component is mounted is provided in the center portion of a silicon substrate, and through electrodes are provided in a silicon substrate under the cavity.
As an example of a method of manufacturing such electronic component package, as shown in FIG. 1A, first, a first mask layer 200 in which opening portions 200x used to form through holes are provided is formed on a silicon wafer 100. Then, as shown in FIG. 1B, the silicon wafer 100 is etched to pass through from its upper surface to its lower surface by using the first mask layer 200 as a mask, and thus through holes TH are formed. Then, the first mask layer 200 is removed.
Then, as shown in FIG. 1C, a second mask layer 300 in which an opening portion 300x used to form a cavity is provided is formed on the silicon wafer 100. Then, as shown in FIG. 1D, the silicon wafer 100 is etched up to the middle of a thickness by using the second mask layer 300 as a mask, and thus a cavity C is formed. Then, the second mask layer 300 is removed. A plurality of package areas are defined on the silicon wafer 100, and the through holes TH and the cavity C are provided in each area.
Then, as shown in FIG. 1E, an insulating layer 400 made of a silicon oxide layer is formed on the whole surface of the silicon wafer 100 by thermally oxidizing the silicon wafer 100. Then, as shown in FIG. 1F, through electrodes 500 are formed in the through holes TH in the silicon wafer 100 by the plating. At this time, the through electrodes 500 are formed in a state that they protrude from an upper surface and a lower surface of the silicon wafer 100 respectively. Then, as shown in FIG. 1G, individual electronic component packages are obtained by cutting the silicon wafer 100.
As the electronic component package utilizing a silicon as the substrate, in Patent Literature 1 (Patent Application Publication (KOKAI) 2004-22990), it is set forth that a metal is filled in through holes in a silicon substrate, then both surface sides of the silicon substrate are planarized by the polishing, and then the silicon substrate is processed by high-pressure annealing, thereby a density and adhesion of the plug metal are improved.
Also, in Patent Literature 2 (Patent Application Publication (KOKAI) Hei 6-169031), it is set forth that an insulating layer made of a relatively soft polymer such as polyimide, and the like is formed on both surfaces of a silicon substrate, then wiring layers are formed thereon, and then an IC chip made of the same material as the silicon substrate is CCB-connected to the wiring layers, thereby a stress applied to connection portions is reduced.
In the above electronic component packages in the prior art, the through electrodes 500 filled in the through holes TH are formed to protrude from a bottom portion of the cavity C, and also their heights are varied on account of the essential characteristic of the plating. Therefore, a coplanarity of the through electrodes 500 on which the electronic component is mounted is not enough. As a result, in some cases a faulty connection is caused in mounting the high-performance electronic component, and such faulty connection becomes a factor of a reduction of yield.
For this reason, the method of improving the coplanarity by planarizing the through electrodes 500 may be considered. However, since the through electrodes 500 are formed after the cavity C is formed, unevenness due to the cavity C exists on the silicon wafer 100. Therefore, it is difficult to planarize the through electrodes 500 in the cavity C by the CMP, or the like. For the same reason, it is extremely difficult to form fine wiring layers connected to the through electrodes 500 on a bottom surface of the cavity C.
Also, in the electronic component package using the silicon substrate, there is a requirement to built in various elements in the silicon substrate. But it is impossible to say that a method of manufacturing such electronic component package has been satisfactorily established.